I. Field of the Disclosure
The technology of the disclosure relates generally to resistive memory, and particularly to resistive memory write driver circuits for providing write currents to resistive memory to perform write operations.
II. Background
Processor-based computer systems include memory for data storage. Memory systems are composed of memory bitcells capable of storing data, wherein the form of the stored data depends on the type of memory employed. In particular, magnetic random access memory (MRAM) is an example of non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) of an MRAM bitcell. Data is stored in an MTJ as a magnetic state, wherein no electric current is required to preserve a stored data value. Thus, an MTJ can store data even when power is not supplied to the MTJ. Conversely, memory that stores data in the form of an electric charge, such as a static random access memory (SRAM), requires power to preserve a stored data value. Thus, because an MTJ may store information even when power is turned off, particular circuits and systems may benefit from employing MRAM.
In this regard, FIG. 1 illustrates an exemplary MRAM bitcell 100 that includes a metal-oxide semiconductor (typically n-type MOS, i.e., NMOS) access transistor 102 integrated with an MTJ 104 for storing non-volatile data. The MRAM bitcell 100 may be provided in an MRAM memory used as memory storage for any type of system requiring electronic memory, such as a central processing unit (CPU) or processor-based system, as examples. The MTJ 104 includes a pinned layer 106 and a free layer 108 disposed on either side of a tunnel barrier 110 formed by a thin non-magnetic dielectric layer. When the magnetic orientation of the pinned and free layers 106, 108 are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientation of the pinned and free layers 106, 108 are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’). Further, the access transistor 102 controls reading and writing data to the MTJ 104. A drain (D) of the access transistor 102 is coupled to a bottom electrode 112 of the MTJ 104, which is coupled to the pinned layer 106. A word line 114 is coupled to a gate (G) of the access transistor 102. A source (S) of the access transistor 102 is coupled to a source line 116, which is coupled to a write driver 118. A bit line 120 is coupled to the write driver 118 and a top electrode 122 of the MTJ 104, which is coupled to the free layer 108.
With continuing reference to FIG. 1, when writing data to the MTJ 104, the gate G of the access transistor 102 is activated by activating the word line 114, which couples a write current (IW) from the write driver 118 on the source line 116 to the bottom electrode 112. The write current (IW) provided by the write driver 118 to the MTJ 104 must be strong enough to change the magnetic orientation of the free layer 108. If the magnetic orientation is to be changed from AP to P, a current flowing from the top electrode 122 to the bottom electrode 112 induces a spin transfer torque (STT) at the free layer 108 that can change the magnetic orientation of the free layer 108 to P with respect to the pinned layer 106. If the magnetic orientation is to be changed from P to AP, a current flowing from the bottom electrode 112 to the top electrode 122 induces an STT at the free layer 108 to change the magnetic orientation of the free layer 108 to AP with respect to the pinned layer 106.
Because the MTJ 104 is a resistive memory element with a given resistance (R(mtj)), applying the write current (IW) to the MTJ 104 during a write operation will generate voltage (V(mtj)) across the MTJ 104 according to V(mtj)=IW*R(mtj). However, the write current (IW) should not exceed a defined current level for the MTJ 104, because the MTJ 104 will incur electrical breakdown if the V(mtj) generated across the MTJ 104 exceeds a certain breakdown voltage (V(bd)). The MTJ 104 is unable to function as a resistive memory element while in a breakdown state. As the tunnel barrier 110 of the MTJ 104 becomes thinner, breakdown of the MTJ 104 occurs at a lower breakdown voltage (V(bd)). Due to process, voltage, and temperature (PVT) variations that can occur during MTJ fabrication, multiple MTJs of the same design and fabrication process may have varying resistance levels R(mtj). Thus, applying the given write current (IW) to MTJs in an MRAM could cause certain MTJs with higher resistances due to process variation to breakdown as a result of generating the breakdown voltage (V(bd)), while other MTJs of the same design with lower resistances would not breakdown.
In this regard, FIG. 2 is a graph 200 illustrating how process variations in MTJ fabrication in an MRAM can cause voltage distributions that may cause certain MTJs to incur breakdown for a given write current (IW). In this regard, the graph 200 in FIG. 2 includes a lower voltage distribution (V(mtj_low)) for MTJs in an MRAM that receive the write current (IW) and that have a lower resistance (R(mtj_low)) as a result of the MTJ fabrication process (i.e., V(mtj_low)=IW*R(mtj_low)). The graph 200 also includes a higher voltage distribution (V(mtj_high)) of MTJs in the MRAM that receive the write current (IW) and that have a higher resistance (R(mtj_high)) as a result of the MTJ fabrication process (i.e., V(mtj_high)=IW*R(mtj_high)). A breakdown voltage distribution (V(bd)) is also shown in the graph 200 in FIG. 2 as the voltage distribution in which breakdown can occur in the MTJs. Notably, the higher voltage distribution (V(mtj_high)) in FIG. 2 is shown as overlapping with the breakdown voltage distribution (V(bd)) in a breakdown overlap region 202. The breakdown overlap region 202 illustrates that certain MTJs within the high voltage distribution (V(mtj_high)) have a high enough resistance (R(mtj_high)) caused by fabrication processes to generate a voltage across the MTJ V(mtj)) as a result of receiving the write current (IW), to exceed the breakdown voltage V(bd), thus resulting in failed write operations. Therefore, it would be advantageous to provide write current to MTJs in an MRAM so as to avoid or reduce electrical breakdown to avoid or reduce write failures.